The invention concerns a multiaddressable highly integrated semiconductor storage, whose storage cells are located at the crossings of word and bit lines and which are addressable by several independent address systems for parallel reading and/or writing.
Storages permitting the parallel reading of two stored words or the simultaneous reading of a particular stored word and the writing of another word into another storage location are known in principle.
A semiconductor storage permitting two or more word lines to be simultaneously addressed is described in DE-OS No. 2 327 062. However, this storage has the disadvantage that the words read are not simultaneously available at the storage output but are combined in the storage to form a logical product. The simultaneous writing of a word into other storage locations is not possible.
Known from U.S. Pat. No. 3 675 218 is furthermore a storage arrangement, wherein information can be written into any random part, while information is read from another part different from the first. Although this solution is technically elaborate, it only permits writing one word and simultaneously reading another. In IBM TDB, Vol. 19, No. 7, December 1976, a storage organization is described permitting the parallel reading of two stored words. From IEEE 1977, "International Solid State Circuit Conference", Feb. 16, 1977, pages 72 and 73, a 32.times.9 ECL dual address register is known permitting two separate parallel read operations of stored words. Besides the apparent access port restrictions the technical means required is the prior art for sensing and selection as well as writing are relatively elaborate and do not permit optimum integration.
The previously described storages, which are addressable in parallel, have the common disadvantage that, unless additional registers or storages are provided, they are not suited for use as high-speed storages in advanced processors. Up-to-date processors comprise, as a rule, high-speed registers, the operation of which is partly concealed and which are partly available to the programmer. With many instructions, two operands are to be read from two different registers and to be fed to the arithmetic unit for processing; the result of this arithmetic operation is stored in one of the registers. In such a known processor, an instruction is executed as follows:
1. Reading two operands from different registers,
2. executing an arithmetical operation, such as an addition, subtraction or multiplication, and
3. feeding the result to one of the registers, i.e., the result is written into one of the registers.
In addition, it is frequently necessary to find a time gap in which other new information, for example, from main storage, can be written into one of the registers. With the storages known so far, which permit addressing only one word or which permit parallel addressing only for reading two words, such operations can only be performed in series or partly in parallel. As a result, storage times accumulate which essentially influence the speed at which an instruction can be executed. To speed up operation, it would be desirable to have a storage, whose ports to the individual registers can be used in parallel, i.e., in the present case to have at least three ports, one read port for each operand and a write port for the result. For addressing these ports to the registers, each of them is provided with an independent addess decoder. As described, register banks with two ports are known from the above-mentioned literature (IEEE 1977). In highly integrated semiconductor technology, in particular bipolar technology, it is relatively difficult and expensive to manage with only one storage cell per bit. In accordance with the two address systems, two cells are generally used for each bit. But these cells must always contain the same information. Care must be taken that information written by an address system into one cell of the pair also reaches the other cell of the pair. In the above-mentioned prior art citation, this is accomplished by coupling the cell pairs in the standby state, i.e., it is only after a cell has been written and is about to assume the standby state, that the coupling impresses the same information into the other cell of the pair. This storage has no third port.
It is the object of the invention to provide a highly integrated semiconductor storage which has at least three ports with independent address decoders which is capable of executing in parallel at least three operations, such as reading a word A, reading a word B and writing a word C, as well as any arbitrary combination of two or individual ones of the three operations, and which eliminates the usual storage and register heirarchy in the processors.